1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a static random access memory device with a low power consumption.
2. Description of the Prior Art
In a static random access memory device (hereinbelow abbreviated to SRAM), generally, DC current flow between terminals of power source of the device continues during a read cycle or a write cycle. It is well known as the reason that the consume power in the SRAM is great. Thus the demand for the SRAM with a low power consumption has been increasing.
One solution to meet this demand, heretofore, has been disclosed in U.S. Pat. No. 4,962,487 issued Oct. 9, 1990 to Suzuki entitled STATIC RANDOM ACCESS MEMORY DEVICE WITH POWER DOWN FUNCTION describing a power down function to reduce the consume current during a write cycle, in which the period to execute an actual write operation is determined not by a period of write cycle which is determined by an external control signal but by a period that pulse signal generating means generates a pulse signal. The period for the actual write operation is forced to be changed to a period for a power down mode by the pulse signal generating means during the write cycle. In U.S. Pat. No. 4,947,379 issued Aug. 7, 1990 to Okuyama entitled HIGH SPEED STATIC RANDOM ACCESS MEMORY CIRCUIT, all word lines and the data output circuits coupled to the bit lines are disabled respectively after the word line enable pulse and the sense amplifier enable pulse were terminated, which reduces the current consumption just in the read cycle.
FIG. 1 shows a recent conventional circuit configuration for the low power consumption. In FIG. 1, a power down timer 15 receives a plurality of address transition detecting signals .phi.ATD1 to .phi.ATDk from an address transition detector 5, a chip selection detecting signal .phi.CSD and a write mode detecting signal .phi.WTD both from a chip selection/write mode detector 13 and a plurality of data input detecting signals .phi.DTD1 to .phi.DTDn from a data transition detector 33, so as to generate a power-down signal .phi.PD with a pulse width established by a pulse elongation circuit 50 as shown in FIG. 2. As the power-down timer 15 employs NOR gates 42, 44 and 46 those receive the address transition detecting signals .phi.ATD1 to .phi.ATDk, the data input detecting signals .phi.DTD1 to .phi.DTDn, the chip selection signal .phi.CSD and the write mode detecting signal .phi.WTD, and further employs a NAND logic gate 48 which receives output signals from the NOR logic gates 42, 44 and 46, the power-down signal .phi.PD may be changed into its complementary logic state in response to a transition with least one out of the detecting signals. As shown in FIG. 1, the power-down signal .phi.PD is used for making a plurality of word lines WL1 to WLn be possible to be conductive thereby, for activating a write switching signal .phi.SWE which connects a data input circuit 29 to a pair of data lines DL and/DL, for generating a sense amplifier enable signal .phi.SAE and also for controlling the data input circuit 29. The read and write operations with the circuit of FIG. 1 will now be described referring to FIG. 3 a timing diagram. During the write cycle, a chip selecting signal CSB and a write enable signal WEB both retain low levels and an output enable signal OEB is high or low level. At the beginning of the write cycle, the chip selection detecting signal .phi.CSD is raised to high level in response to the chip selecting signal CSB falling to low level, and the address transition detecting signal .phi.ATDi (i=1 to k) to high level in response to a transition of an address bit Ai (i=1 to k). The write mode detecting signal .phi.WTD goes to high level in response to the write enable signal WEB falling to low level, and the data input detecting signal .phi.DTDi (i=1 to n) to high level in response to a transition of an input data bit. Thus, the power-down signal .phi.PD is generated from the power-down timer 15 shown in FIG. 2, according to the logic status of the detecting signals .phi.CSD, .phi.WTD, .phi.ATDi and .phi.DTDi.
Since the word line WLi (i=1 to n) as a selected one can be activated while the power-down signal .phi.PD having a predetermined pulse width established by the pulse elongation circuit 50 retains low level, an activation for the word line WLi is terminated when the power-down signal .phi.PD is raised to high level. At this time, the data input circuit 29 is disabled and the write switching signal .phi.SWE becomes low level. As a result, a current flowing toward the memory cells and from the data input circuit 29 is suspended therein.
In a read cycle in which the chip selecting signal CSB, the write enable signal WEB and the output enable signal OEB stay on low, high and low levels, respectively. And the sense amplifier enable signal .phi.SAE is dependent upon the power-down signal .phi.PD being placed on low level for a period by the predetermined pulse width. Therefore, as figured in the write cycle, the word line WLi which has been selected and the sense amplifier 35 are disabled after a latch operation with a data output buffer 37, responding to the power-down signal .phi.PD rising to high level.
The circuit as illustrated in FIG. 1, however, has some problems relevant to an abnormal performance that would be revealed throughout the read cycle. Referring to FIG. 4 which shows timing configurations at an initial state when a power supply voltage is beginning to be applied from an external system, there are no transitions with the chip selecting signal CSB, the write enable signal WEB, the address bits, the output enable signal OEB, and with the input data bits. That phenomenon causes the detecting signals .phi.ATDi, .phi.CSD, .phi.WTD and .phi.DTDi all not to be changed from their current states, right resulting in an inactivation of the power-down signal .phi.PD. Thus, it may be impossible to write data into a memory cell corresponding to a normal address because any word line or data line can not be conductive due to the power-down signal's null condition. Predictable result is that abnormal data could be read out from inefficient memory cells during the read cycle.